1. Field of the Invention
The present invention relates to a semiconductor storage device and its cell activation method. In particular, the present invention relates to a semiconductor storage device having an SRAM (Static Random Access Memory) as storage cells and its cell activation method.
2. Description of Related Art
Owing to their high process compatibility, static random access memories (hereinafter simply referred to as “SRAMs”) have been integrated into semiconductor devices with various function blocks including CPUs in the past. The high packing density and the high operating speed of semiconductor devices have been achieved by miniaturizing transistors, which are the basic elements of the semiconductor devices. Therefore, SRAMs, which are integrated into such semiconductor devices, are also desired to be miniaturized to achieve the higher packing density and the higher operating speed.
However, in recent years, as the CMOS process has been miniaturized, element variations in transistors constituting SRAM cells has been increasing. This increase in element variations has been causing a problem in read operations in SRAM cells that the reading characteristic deteriorates and the stored data is thereby corrupted. Further, it also has been causing a problem in write operations in SRAM cells that the writing characteristic deteriorates. Further, because of these deteriorations in characteristics, there has been another problem that yields in large-scale SRAM manufacturing are lowered. To suppress this decrease in yields, it is necessary to increase the size of transistors constituting SRAM cells to reduce the element variations. However, the increase in transistor size causes a problem that the size of SRAM cells becomes larger.
Accordingly, K. Zhang, et al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply” ISSCC2005 (K. Zhang, et al.) discloses a technique to solve this problem. In K. Zhang, et al., the potential of word line signals output from a word line control circuit is controlled so as to be lower than the power supply potential of SRAM cells. In this way, the technique disclosed in K. Zhang, et al. can improve the reading characteristic and thereby suppress the corruption of stored data in read operations of the SRAM cells. Further, the potential of the word line signals is controlled so as to be lower than the power supply potential of the SRAM cells in write operations of the SRAM cells. In this way, the technique disclosed in K. Zhang, et al. can improve the writing characteristic during write operations in the SRAM cells.
Further, Japanese Unexamined Patent Application Publication No. 2006-040466 discloses a technique to improve a reading characteristic and a data retention characteristic. In Japanese Unexamined Patent Application Publication No. 2006-040466, the potential of word line signals is controlled to two levels consisting of first and second power supply potentials in order to perform stable access operations for a high resistance load type SRAM. A reading operation is performed while the potential of the word line signal is at the first power supply potential. Further, after a potential difference between a pair of bit lines is amplified by a sense amplification circuit, the potential of the word line signal is controlled to the second power supply potential to perform a writing operation. In SRAM cells in which the wiring operation is not performed, i.e., in pseudo-read cells, the stored data is written back to the cells by the sense amplification circuit. Therefore, the writing operation is performed without causing any corruption of the stored data in the pseudo-read cells.